How to use a simple Makefile
Define a target
A Makefile rule names a target, its prerequisites, and a tab-indented recipe.
CC = cc
CFLAGS = -std=c17 -Wall -Wextra -Wpedantic -g
app: main.o calculator.o
$(CC) $(CFLAGS) main.o calculator.o -o app
Compile object files
Separate rules rebuild only sources whose prerequisites changed. List headers so edits trigger recompilation.
main.o: main.c calculator.h
$(CC) $(CFLAGS) -c main.c
calculator.o: calculator.c calculator.h
$(CC) $(CFLAGS) -c calculator.c
Add a clean target
A phony target represents an action rather than a generated file. Keep removal limited to known build products.
.PHONY: clean
clean:
rm -f app main.o calculator.o
Run the build
Run make to build the first target, make clean to remove outputs, and make CC=clang to select Clang.
make
./app
make clean
make CC=clang